Design Verification Engineer job in AMD, Canada.

 Design Verification Engineer - Canada 

JOB SUMMARY 

Location: Markham, Canada

Category: Engineering

Job Id: 35760

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Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. 

We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance.

THE ROLE:

This is an exciting opportunity to work in the AMD PCIe IP Verification Team as Senior Verification Engineer. The candidate will have an opportunity to work on state-of-the-art verification environment using UVM verification methodology. 

We are looking for dynamic candidates with excellent communication skills. The role also provides opportunity to work on various aspects of verification such as performance verification, power aware verification besides functional verification.

THE PERSON:

We are looking for a dynamic candidate who will have great opportunity to work on the state-of-the-art products with leading verification methodology. 

Take your current verification expertise and apply that to state of the are data center products involving complex protocols like PCIE, CXL, networking etc. We are looking for team players with good communication skills. 

KEY RESPONSIBILITIES:

• Create block level verification plan, test plans and full chip test plan

•Develop block level test bench and tests in UVM methodology including scoreboard

• Work on a new UVM based PCIe transaction Layer test-bench

• Work with designers to get coverage closure

• Integrate VIPs as needed

PREFERRED EXPERIENCE:

• Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology

• Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and functional coverage with design team

• Good understanding of object-oriented programming concepts

• Prior experience with PCIE Protocol

• Prior experience in verifying is system/sub system level involving multiple blocks

• Prior experience with protocols such as AXI, APB, AHB etc.

• Programming in scripting languages like Python, TCL and Perl

• Excellent communication skills

• Good problem-solving skills and analytical ability

• Familiarity with EDA tools for simulation, debugging, coverage analysis

Desirable Qualifications:

Exposure to formal verification methodologiesPrior experience with verifying PCIE IPSystem level understanding of PCIE based systemsPrior experience in integrating Verification IPs (VIP) & UVC in verification environmentPrior experience in bringing up gate level simulation and debugging issues

ACADEMIC CREDENTIALS:

• PhD in Electrical Engineering or Computer Engineering or related equivalent with Or

• Master's Degree in Electrical Engineering/Computer Engineering/related equivalent Or

• Bachelor's Degree in Electrical Engineering/Computer Engineering/related equivalent

LOCATION: Markham/ Ottawa

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

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